The present invention relates to booster circuits used for nonvolatile semiconductor memories and semiconductor integrated circuits.
In recent years, in nonvolatile semiconductor memories such as flash EEPROMs, booster circuits have been widely used for supply of various levels of high voltages for write, erase and read operations. In particular, as such booster circuits, used extensively are threshold-offset type booster circuits driven with a four-phase clock signal that are excellent in low-voltage operation and boost efficiency.
A conventional four-phase clock driven threshold-offset type booster circuit will be described with reference to FIG. 21. The booster circuit of FIG. 21 is a four-stage booster circuit including four booster cells 1a to 1d connected in series. A rectifying transistor Md is connected to the output of the final-stage booster cell 1d for outputting an output voltage VPP. A limit circuit 2 and a smoothing capacitor Co are connected to the output of the rectifying transistor Md. The limit circuit 2 is essentially composed of a read Zener diode DZ1 having a breakdown voltage of 5V used for read operation, a rewrite Zener diode DZ2 having a breakdown voltage of 10V used for write/erase operations, and a switch 3. By controlling the switch 3 with a switch control signal ACTH, the output voltage VPP is switched between 10V and 5V.
Each of the booster cells 1a to 1d is driven with two boost clock signals having different phases (CLK1 and CLK3 or CLK2 and CLK4) as shown in FIG. 22. The clock signals CKL1 to CKL4 are square waves having predetermined xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d durations and cycles. The booster cells 1a to 1d have an identical configuration to each other, which may be that disclosed in Japanese Laid-Open Patent Publication No. 2001-268893, for example. FIG. 23 shows an example of internal configuration of the final-stage booster cell 1d. Referring to FIG. 23, the booster cell 1d includes an N-channel charge-transfer transistor M1, an N-channel switching transistor M2 and two boost capacitors C1 and C2. The booster cell 1d receives the clock signal CLK4 at one clock terminal CLKS, an inverted signal NCLK2 of the clock signal CLK2 at the other clock terminal CLKM, and a boosted voltage from the preceding-stage booster cell 1c at an input terminal VIN, and outputs a boosted voltage from an output terminal VO to the rectifying transistor Md.
The operation of the conventional booster circuit having the configuration described above will be described.
In the booster circuit of FIG. 21, charge is stored in the boost capacitors C1 of the booster cells sequentially, starting from the first-stage booster cell 1a to the second-stage, third-stage and fourth-stage cells, to finally obtain an arbitrary high voltage. For example, a voltage boosted in the third-stage booster cell 1c is transferred from the boost capacitor C1 of the third-stage booster cell 1c to the boost capacitor C1 of the fourth-stage booster cell 1d. During this voltage transfer, in the final-stage booster cell 1d, the boost clock signal CLK4 input to the boost capacitor C2 is changed from the ground potential to the supply potential at timing T6 shown in FIG. 22, so that the gate voltage of the charge-transfer transistor M1 is sufficiently increased. With the sufficiently high gate voltage, it is possible to prevent voltage drop occurring when the boosted voltage is transferred from the third stage to the boost capacitor C1 via the charge-transfer transistor M1. Thereafter, at timing T8, the inverted clock signal NCLK2 input to the clock terminal CLKM is changed from the ground potential to the supply potential (that is, the clock signal CLK2 is changed from the supply potential to the ground potential), so that the boosted voltage transferred to the boost capacitor C1 is further boosted. By repeating this boost operation sequentially in the first to fourth stages, a boosted voltage higher than the supply voltage Vcc can be generated. In the fourth-stage booster cell 1d, at timing T8 in the next cycle, in which the inverted clock signal NCLK2 input to the clock terminal CLKM of the fourth-stage booster cell 1d is changed from the ground potential to the supply potential (that is, the clock signal CLK2 is changed from the supply potential to the ground potential), the gate-source voltage Vgs of the switching transistor M2 exceeds the threshold voltage Vth of this transistor, turning ON the switching transistor M2. In this state, the charge at the gate of the charge-transfer transistor M1 can be drawn to the input terminal VIN, and thus the gate voltage of this transistor decreases.
The limit circuit 2 can change the output voltage VPP to a predetermined voltage in response to the switch control signal ACTH. To state specifically, during write operation requiring a high voltage, the switch control signal ACTH is asserted, to connect the rewrite Zener diode DZ2 to the output terminal of the booster circuit so that the output voltage VPP is clamped to 10V. During read operation requiring a low voltage, the switch control signal ACTH is negated, to connect the read Zener diode DZ1 to the output terminal of the booster circuit so that the output voltage VPP is clamped to 5V. In this way, the output voltage VPP of the booster circuit can be changed according to the operation mode before supply for use.
However, it has been found that, as the voltage level of the power supply is made lower in the future, the conventional booster circuit described above will have a problem as follows when the output boosted voltage is abruptly switched from a high voltage to a low voltage, such as during a specific mode transition including transition from the data rewrite mode to the read mode and transition from the rewrite mode to the program verify mode, and during an instantaneous power interruption.
That is, referring to FIG. 24, during a specific mode transition or during an instantaneous power interruption as described above, in which the boosted voltage is switched to a low voltage, the source voltage Vs of the ON-state charge-transfer transistor M1 of the fourth-stage booster cell 1d abruptly decreases, and with this, the drain voltage Vd also abruptly decreases, resulting in that the source voltage Vs and the drain voltage Vd become roughly an identical potential. Thus, the gate voltage Vg of the switching transistor M2 and the source voltage Vs of the same transistor (that is, the drain voltage Vd of the charge-transfer transistor M1) become an identical potential. As a result, the switching transistor M2 is cut off, leaving the gate of the charge-transfer transistor M1 at a high voltage.
If the power supply is at a high voltage, that is, the amplitude of the boost clocks CLK1 to CLK4 is large, the fourth-stage booster cell 1d will operate as follows. When the inverted clock NCLK2 of the boost clock CLK2 is input to the terminal CLKM of the booster cell 1d, the gate voltage Vg of the switching transistor M2 becomes sufficiently high due to the H level of the inverted clock NCLK2. Therefore, the gate-source voltage Vgs of the switching transistor M2 exceeds the threshold voltage, turning ON the switching transistor M2. As a result, the charge at the gate of the charge-transfer transistor M1 is released, preventing the gate from being left at a high voltage.
On the contrary, if the power supply is at a low voltage, the amplitude of the boost clocks CLK1 to CLK4 is small. Therefore, when the inverted clock NCLK2 of the boost clock CLK2 is input, the gate voltage Vg of the switching transistor M2 fails to become sufficiently high due to the H level of the inverted clock NCLK2. Thus, the gate-source voltage Vgs of the switching transistor M2 may not exceed the threshold voltage Vt. In this case, the switching transistor M2 remains in the cut-off state irrespective of changes of the boost clocks CLK2 and CLK4, leaving the gate of the charge-transfer transistor M1 at a high voltage. As a result, the gate-source voltage Vgs of the charge-transfer transistor M1 is kept greater than the threshold voltage Vt (0.51 V) and thus the charge-transfer transistor M1 remains in the ON state. This causes failure of desired boost operation, degrades the current supply capability of the booster circuit, and decreases the boosted voltage VPP. As a result, good normal operation of a circuit to which the boosted voltage is supplied may not be secured.
As described above, the conventional booster circuit has a problem that, when the amplitude of the boost clock signals CLK1 to CLK4 is small due to a low voltage of the power supply, normal boost operation may fail and the current supply capability of the booster circuit may degrade after a specific mode transition or during a restart after an instantaneous power interruption as described above.
An object of the present invention is providing a highly reliable booster circuit capable of securing ON/OFF of a charge-transfer transistor as desired to enable stable boost operation under use of low-voltage power supply even during a transition from a mode for output of a high boosted voltage to a mode for output of a low boosted voltage, during a restart after an instantaneous power interruption or the like.
To attain the object described above, according to the present invention, the gate voltage of a charge-transfer transistor is forcibly reset to a predetermined reset potential of which the absolute value is higher than the supply voltage.
The booster circuit of the present invention includes n-stage (n is an integer equal to or more than 2) booster cells connected in series, at least the final-stage booster cell among the n booster cells including: a charge-transfer transistor for transferring an output voltage received from the preceding stage to the following stage; an output voltage boost capacitor having one electrode connected to the output of the charge-transfer transistor and the other electrode receiving a first clock signal having a predetermined phase; a gate voltage boost capacitor having one electrode connected to the gate of the charge-transfer transistor and the other electrode receiving a second clock signal having a predetermined phase; and a switching transistor for connecting the gate of the charge-transfer transistor to the input terminal of the charge-transfer transistor, wherein the booster circuit includes reset means for receiving a control signal and resetting a gate voltage of the charge-transfer transistor of at least the final-stage booster cell to a predetermined reset potential based on the control signal, the absolute value of the predetermined reset potential being higher than the supply voltage.
In the booster circuit described above, preferably, the control signal is output in an event that the gate voltage of the charge-transfer transistor of at least the final-stage booster cell remains higher than an input voltage of the charge-transfer transistor by a value equal to or greater than a predetermined voltage, and in this event, the reset means resets the gate voltage of the charge-transfer transistor of at least the final-stage booster cell to the predetermined reset potential.
In the booster circuit described above, preferably, the control signal is output in an event that the gate voltage of the charge-transfer transistor of at least the final-stage booster cell remains higher than the input voltage and an output voltage of the charge-transfer transistor by a value equal to or greater than a predetermined voltage.
Preferably, the predetermined voltage is a voltage equal to a threshold voltage of the charge-transfer transistor.
In the booster circuit described above, preferably, the control signal is output to the reset means during a specific mode transition, and during the specific mode transition, the reset means resets the gate voltage of the charge-transfer transistor of at least the final-stage booster cell to a predetermined reset potential.
In the booster circuit described above, preferably, the control signal is output to the reset means during a startup of the booster circuit, and during the startup, the reset means resets the gate voltage of the charge-transfer transistor of at least the final-stage booster cell to a predetermined reset potential.
In the booster circuit described above, preferably, the predetermined reset potential for the gate voltage of the charge-transfer transistor is set at a voltage value higher than the supply voltage when positive-going boost operation is performed.
In the booster circuit described above, preferably, the resetting of the gate voltage of the charge-transfer transistor to a predetermined reset potential by the reset means is performed for a plurality of booster cells, and the predetermined reset potential for the gate voltage of the charge-transfer transistor of one of the plurality of booster cells is set at a potential equal to or higher than the predetermined reset potential for the preceding-stage booster cell when positive-going boost operation is performed.
In the booster circuit described above, preferably, the reset means includes: boost means for receiving the control signal, amplifying the amplitude of the control signal, and outputting the amplified signal; and a reset circuit for receiving the output of the boost means and resetting the gate voltage of the charge-transfer transistor of at least the final-stage booster cell to a predetermined reset potential exceeding the supply voltage.
In the booster circuit described above, preferably, the reset means resets the gate voltage of the charge-transfer transistor of at least the final-stage booster cell to a predetermined reset potential equal to a voltage input to the charge-transfer transistor.
Preferably, the booster circuit described above further includes control signal generation means for receiving a predetermined control signal originally generated for control of the booster circuit, detecting a change of the predetermined control signal, asserting the control signal for a set time period, and outputting the control signal to the reset means.
Alternatively, the booster circuit of the present invention includes n-stage (n is an integer equal to or more than 2) booster cells connected in series, at least the final-stage booster cell among the n booster cells including: a charge-transfer transistor for transferring an output voltage received from the preceding stage to the following stage; an output voltage boost capacitor having one electrode connected to the output of the charge-transfer transistor and the other electrode receiving a first clock signal having a predetermined phase; a gate voltage boost capacitor having one electrode connected to the gate of the charge-transfer transistor and the other electrode receiving a second clock signal having a predetermined phase; and a switching transistor for connecting the gate of the charge-transfer transistor to the input terminal of the charge-transfer transistor, wherein the booster circuit includes automatic reset means for resetting a gate voltage of the charge-transfer transistor to a predetermined reset potential when the voltage difference between the gate voltage and an input voltage of the charge-transfer transistor is greater than a predetermined potential difference.
In the booster circuit described above, preferably, the automatic reset means includes: switch means for connecting the gate of the charge-transfer transistor to the input terminal of the charge-transfer transistor; and a control circuit for comparing the gate voltage and the input voltage of the charge-transfer transistor to obtain a voltage difference, activating the switch means when the voltage difference is greater than a predetermined potential difference, to connect the gate of the charge-transfer transistor to the input terminal of the charge-transfer transistor.
In the booster circuit described above, the booster circuit preferably performs negative-going boost operation.
Conventionally, in an event that the output voltage of the booster circuit abruptly changes from a high boosted voltage to a low boosted voltage, such as during a mode transition or during an instantaneous power interruption, under use of a low-voltage power supply, the following problem may occur. That is, the switching transistor remains in the cut-off state, and thus the gate of the charge-transfer transistor is left at a high potential. Therefore, the potential difference between the gate voltage and the input voltage of the charge-transfer transistor becomes equal to or greater than the threshold voltage of the charge-transfer transistor, and as a result, the charge-transfer transistor remains in the ON state. However, according to the present invention, the control signal is sent to the reset means after the mode transition or during the restart, to forcibly reset the gate voltage of the charge-transfer transistor to a predetermined reset potential of which the absolute value is higher than the supply voltage. Therefore, the problem that the charge-transfer transistor remains in the ON state is prevented, and normal boost operation is secured after a mode transition or during a restart. Thus, stable current supply capability is ensured, and a highly reliable booster circuit is attained.
According to the present invention, in particular, in the positive booster circuit for boosting a positive voltage, the reset potential for the gate voltage of the charge-transfer transistor is set at a positive voltage higher than the positive supply voltage. Therefore, waste of the positive boosted charge due to the reset operation can be suppressed, and the time required to reach the steady state of the boost operation can be shortened. Thus, reduction of power consumption and shortening of the wait time until voltage stability can be attained.
According to the present invention, in particular, the reset potential for the gate voltage of the charge-transfer transistor of a booster cell is set at a potential equal to or higher than the reset potential set for the preceding-stage booster cell. Therefore, waste of the boosted charge due to the reset operation can be further suppressed, and the time required to reach the steady state of the boost operation can be further shortened. Thus, further reduction of power consumption and further shortening of the wait time until voltage stability can be attained.
According to the present invention, in particular, the reset potential for the gate voltage of the charge-transfer transistor is set at a potential equal to or higher than the supply voltage. Therefore, the charge remaining at the gate of the charge-transfer transistor is returned to the supply terminal during the reset operation. This further decreases the current consumption.
According to the present invention, in particular, the reset potential for the gate voltage of the charge-transfer transistor is equal to the input voltage of the same charge-transfer transistor. Therefore, waste of the boosted charge due to the reset operation can be minimized, and the time required to reach the steady state of the boost operation can be most shortened. Thus, reduction of power consumption and shortening of the wait time until voltage stability can be attained effectively.
According to the present invention, in particular, the reset operation for the gate is voltage of the charge-transfer transistor can be performed using the existing control signal. This enables the reset operation with a simple circuit configuration.
According to the present invention, in particular, the automatic reset means automatically operates when the voltage difference between the gate voltage and the input voltage of the charge-transfer transistor is greater than a predetermined value, to automatically reset the gate voltage of the charge-transfer transistor to the input voltage of the transistor. Therefore, even in an event of abrupt change of the output voltage from a high boosted voltage to a low boosted voltage, such as during a mode transition or during an instantaneous power interruption of the booster circuit, it is possible to prevent reliably the problem of the charge-transfer transistor remaining in the ON state that would otherwise be likely to occur in such an event. In addition, waste of the boosted charge due to the reset operation is suppressed. Normal boost operation is therefore secured with low power consumption even after the mode transition or during the restart. Thus, stable current supply capability is ensured, and a highly reliable booster circuit is attained.
According to the present invention, in particular, in negative-going boost operation, during abrupt change of the output voltage from a high negative boosted voltage to a low negative boosted voltage, such as during a mode transition or during an instantaneous power interruption, the problem that the charge-transfer transistor remains in the ON state is prevented. Thus, normal boost operation is secured after the mode transition and during the restart.